Science

NASA and Microchip Launch Partnership for Next-Generation Space Computing

The High-Performance Spaceflight Computing project, led by NASA's Space Technology Mission Directorate, integrates computing and networking to reduce costs while offering radiation-hardened solutions for missions to the Moon, Mars and beyond.

Author
Mara Ellison
Science and Space Editor
Published
Draft
Source: NASA News Releases · original
NASA, Industry Advance High Performance Spaceflight Computing
A new public-private collaboration aims to deliver processors with over 100 times the computing power of current systems for deep-space exploration.

NASA and industry partner Microchip Technology Inc. have announced a public-private partnership to develop High-Performance Spaceflight Computing. This initiative targets a next-generation system-on-chip capable of delivering more than 100 times the computing capability of existing space processors. The project is being led by the Space Technology Mission Directorate, with specific guidance and development support coming from NASA's Langley Research Center and the Jet Propulsion Laboratory.

The driving force behind this collaboration is the increasing complexity and duration of future space missions. While legacy radiation-hardened processors, which trace their lineage back to the Apollo Guidance Computers of the 1960s, have successfully powered Mars rovers and orbiters, upcoming explorations require greater autonomy, data processing power, and resilience. The new technology addresses these needs by integrating computing and networking into a single device, a design choice intended to significantly reduce system costs and power consumption.

The processor family is designed with two distinct variants to suit different operational environments. A radiation-hardened version is built for geosynchronous and deep-space missions, including long-duration travels to the Moon, Mars and beyond, ensuring operation in harsh environments. Conversely, a radiation-tolerant version is tailored for the commercial space sector, providing fault tolerance and cybersecurity for satellites operating in low Earth orbit.

Scalability is a central feature of the architecture, allowing unused functions to power down and optimising energy efficiency for critical operations. This design enables spacecraft to process massive volumes of data onboard and make real-time autonomous decisions. Examples include high-speed navigation for rovers and the filtering of scientific images, tasks that previously might have required data to be transmitted back to Earth for processing.

Beyond space exploration, the technology is designed with a dual-use platform for Earth-based industries. By adopting high-performance computing, network switching, high-reliability and cybersecurity technologies, the processors enable mission-critical edge computing for sectors such as automotive, aviation, energy grids, medical equipment and industrial systems. This approach aims to strengthen domestic industrial capabilities and reduce risk and cost for both government and commercial users.

The High-Performance Spaceflight Computing project represents a nationwide effort anchored by NASA, Microchip and a broad ecosystem of academic and industry partners. The initiative seeks to reinforce U.S. leadership in spaceflight computing, strengthen supply chain resilience and security, and stimulate regional economies while driving innovation and high-tech workforce development across the nation.

Continue reading

More from Science

Read next: NASA to showcase space science and Artemis at 2026 FIFA World Cup Fan Festival in Houston
Read next: NASA’s INCUS satellites complete testing ahead of 2027 launch
Read next: NASA’s X-59 Breaks Sound Barrier in First Supersonic Flight