RISC-V Chief Architect Declares Enterprise Data Centre Entry 'Inevitable' at Bologna Summit
With major tech firms integrating the open-standard ISA into server-class systems, RISC-V International signals a shift from embedded devices to high-performance computing.
Krste Asanović, chief architect at SiFive and RISC-V International, declared the open-standard instruction set architecture’s entry into the enterprise data centre market as inevitable during his keynote at the RISC-V Summit Europe 2026 in Bologna. Speaking to an audience of industry leaders, Asanović described the ecosystem’s state as “strong” and identified the deployment of high-performance RVA23 silicon as the defining theme of the year. The standard, officially approved in October 2024, marks a historic inflection point for server-class systems, moving the technology beyond its traditional stronghold in embedded electronics and microcontrollers.
Major technology companies and chipmakers, including Qualcomm, Nvidia, Meta, Google, and Alibaba, are now integrating RISC-V technology into their products. Asanović noted that server-class systems are “actually starting to appear,” driven by the promise of RVA23 silicon. He emphasised that hyperscalers and data centre owners are investing in RISC-V as an alternative to incumbent architectures, citing greater flexibility in both technical features and business models. The alignment between hardware developers and software engineers under the RVA23 framework allows for testing on real hardware rather than relying on emulators, a significant step for the standard’s maturity.
To bridge the gap between basic software compatibility and competitive performance, Asanović introduced new optimisation guidance options, specifically Oilsm and Ovlt. Previously, RISC-V ISA strings described instruction functions but not execution speeds, leading to inefficiencies such as slow trap-and-emulate methods for misaligned memory accesses. Oilsm, for instance, allows software to assume hardware will handle misaligned scalar and vector accesses quickly. Asanović clarified that these are not mere suggestions but inform the software ecosystem that code should be optimised for high-performance implementations, raising the bar for hardware vendors.
Security remains a critical component of the architecture’s enterprise expansion. The RISC-V International consortium is advancing a suite of new security extensions, with the most significant being the redefinition of Capability Hardware Enhanced RISC Instructions (CHERI). Rather than a simple extension, CHERI has been created as an entirely new base ISA, designated as RV32Y and RV64Y. This approach allows for invasive memory safety innovations without disturbing other parts of the architecture. Asanović argued that this creates a single global open standard for CHERI systems, preventing fragmentation while enabling developers to innovate freely.
Concurrently, the community is finalising the RVM ISA profile for microcontrollers to prevent software fragmentation caused by extreme specialisation. Asanović warned engineers against stripping core features for marginal silicon savings, arguing that standardisation reduces complexity compared to legacy ISAs. He referenced Ivan Sutherland’s 1968 “Wheel of Reincarnation” concept to explain how RISC-V’s modularity allows it to scale from AI accelerators to embedded devices. With expanding digital signal processing capabilities and a focus on shared software development, RISC-V aims to reduce training time and costs while capturing the burgeoning AI accelerator market.
