Researcher Documents Extreme CPU Latency Techniques in 'Assembly Hall of Shame'

A new research project hosted on GitHub, titled 'asm-hall-of-shame', has documented techniques designed to maximise single-instruction CPU latency. Authored by researcher Christopher Domas, the repository serves as a counterpoint to standard performance optimisation, seeking to identify the lowest possible performance floor for individual processor instructions. The project was published under the user handle 'xoreaxeaxeax' and details specific assembly strategies that induce extreme performance degradation.

Testing was conducted on Intel Core i7-8559U and AMD Ryzen 7 5800H processors, revealing how specific hardware behaviours can be exploited to slow execution. One primary strategy involves saturating the PCIe root complex with non-posted transactions. By using a fleet of hammer cores to pound a different high-latency memory-mapped I/O register with tight reads, the fabric is congested, forcing a 512-byte FPU state load to queue behind contending traffic.

The research also highlights methods for triggering microcode assists, which significantly increase execution time. Techniques include using denormal numbers to force floating-point operations through slower microcode paths rather than standard hardware execution. On the Intel Core i7-8559U, researchers identified a "lonnnnnng nop" strategy to extend the duration of a no-operation instruction, alongside methods to drive the longest path through the divider microcode using specific dividend and divisor values.

Further findings include the exploitation of hardware entropy pool depletion. By executing tight loops, the research demonstrates that the hardware entropy source can be drained faster than it can be refilled, causing subsequent calls to stall. Other techniques involve aligning lock-prefixed operands to straddle cache-line boundaries, forcing the CPU to assert an external bus lock instead of using faster cache-coherence protocols.

The repository notes that some methods are technically disallowed but functional in tests, such as using 16-byte and 32-byte unaligned memory-mapped I/O reads to access unknown GPU registers. While the project focuses on academic exploration of hardware limits, it includes warnings that these techniques may cause system instability. A specific claim notes that leveraging extended AVX state in Sapphire Rapids with a similar approach could result in latency of approximately one trillion cycles.