Developer embeds experimental RISC-V processor in Qwen model
Qwenputer uses the model’s Gated DeltaNet state as addressable memory. Its developer reports exact arithmetic and passing RISC-V tests, while noting the system remains slow and requires a driver.
A developer has described Qwenputer, an experimental version of Qwen3.5 4B with a deterministic 32-bit RISC-V processor compiled into additional model weights. The design uses Gated DeltaNet state as addressable memory, allowing the processor to run during model forward passes.
The account, published on the developer’s blog and shared by Hacker News, says the processor can perform arithmetic and run C and MicroPython without external tool calls. A small RvChat driver is still required to load firmware and manage execution trace tokens; the model does not yet work with a plain generate() call.
The developer reports that the RV32IM core passes official RISC-V tests, matches QEMU on programs and completed 18 million instructions without error. On a long-integer arithmetic benchmark, Qwenputer scored 100%, compared with 48.6% for base Qwen. The developer also reports zero mismatches across about 230,000 checked output positions.
An experimental file system stores data in the model’s state and can retain it between conversations when that state is saved and reloaded. The developer reports 90% success on questions about facts changed between chats, compared with 30% when prior conversations were pasted in.
The project has substantial limits: each CPU instruction uses several decoded tokens, and large calculations take seconds rather than milliseconds. The checkpoint is reported to be 18.8GB, and the file system remains experimental. The performance figures are claims from the developer’s post; the supplied material does not establish independent replication.
