IBM unveils ‘nanostack’ architecture claiming world’s first sub-1 nanometer chip technology
The technology, presented at the IEEE Symposium on VLSI Technology and Circuits, targets commercial production within a decade through foundry partnerships.
IBM has announced the development of a new “nanostack” chip architecture, describing it as the world’s first sub-1 nanometer technology. The design vertically stacks transistors to achieve a density of nearly 100 billion on a chip the size of a human fingernail, offering potential improvements of 50 per cent in computing performance or 70 per cent in energy efficiency compared to its previous 2-nanometer generation. The technology also features a staggered-channel design for static random-access memory (SRAM) that reduces cell height by 40 per cent. While IBM does not manufacture commercial chips, it expects the technology to enter production within five to ten years through partnerships with foundries such as Rapidus or Samsung.
The company describes the new chip technology as being built at the 0.7-nanometer node, which it has named the 7 angstrom node. IBM presented the nanostack transistor architecture at the 2025 IEEE Symposium on VLSI Technology and Circuits in Kyoto, Japan, and researchers demonstrated a 40 per cent improvement in scaling for SRAM at the VLSI 2026 symposium. IBM declined to name specific partners for the new sub-1-nanometer technology, though it previously partnered with Rapidus and Samsung for 2-nanometer chips.
Jay Gambetta, director of IBM Research and IBM Fellow, described the new chip technology as “pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.” He noted that the improvement comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers. Gambetta explained that SRAM scaling has fallen off drastically in recent generations, with improvements of just a few percent between the 3-nanometer and 2-nanometer chip generations.
The basic unit of the nanostack architecture consists of two transistors stacked and bonded together, with each transistor comprising three nanosheets individually 5 nanometers thick. There is approximately 9 nanometers of distance separating each nanosheet. The staggered-channel design for the chip’s SRAM bit cells reduces overall cell height by 40 per cent, enabling more SRAM to be squeezed into the same chip space. This is particularly relevant for AI workloads, which require higher bandwidth and high efficiency.
Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, stated that nanosheet has become the foundation of the next generation of transistor scaling and is adopted by all leading foundries for most 3-nanometer chips and all 2-nanometer chips. Bu expects that commercial chips made at the sub-1-nanometer node and incorporating the newest nanostack architecture could begin production as early as in the next five years and most likely within a decade. He added that it will replace nanosheet as today’s mainstream in leading foundries, whether for CPUs or GPUs.
